ISSCC 2009 / SESSION 4 / HIGH - SPEED DATA CONVERTERS / 4 . 4 4 . 4 A 5 b 800 MS / s 2 mW Asynchronous Binary - Search ADC in 65 nm CMOS

Digital wireless communication applications such as UWB and WPAN necessitate low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suffer from high power consumption and large area overhead. On the contrary, SAR ADCs have low power dissipation and occupy a small area. However, a SAR ADC needs several comparison cycles to complete one conversion, which limits its conversion speed. The highest single-channel operation speed of previously reported SAR ADCs is 625MS/s [1]. The ADC in [1] utilizes a 2b/step structure. For non-multi-bit/step SAR ADCs, the highest reported conversion rate is 300MS/s [2]. The structure of a comparator-based binary-search ADC is between that of flash and SAR ADCs [3]. Compared to a flash ADC (high speed, high power) and a SAR ADC (low speed, low power), a binary-search ADC achieves balance between operation speed and power consumption. This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. The maximum conversion speed of this ADC is 800MS/s at a cost of 2mW power consumption.